Course Title: MPC5644A (Andorra) Power Architecture
Target Applications: Industrial and Automotive 1-4 Cylinder gasoline direct injection engines, entry-level diesel engines and entry level transmissions.
Course Description: A 3-day workshop that covers e200 Power Architecture core, including system exceptions & interrupt handling. It covers the Core memory management unit (MMU) operation and programming. Memory protection, cross-bar switch and all internal/external buses are covered. Also included are details of all on-chip peripherals with emphasis on device timers such as the enhance Time Processor Unit (eTPU), enhanced Modular I/O System (eMIOS).
It includes coverage of the enhanced Queued Analogue-to-Digital Converter (eQADC) operation and programming along with Decimation filters and Reaction Unit operation. It also covers all serial communication interfaces: CAN Bus (FlexCANs), DSPIs, ESCIs (LINFlex) with software examples and optional hands-on labs.
After completing the workshop, the participant will understand the basic concepts of the Power Architecture and all major functional blocks of the MPC5644A device. With hands-on examples and development tools, the participant will be able to program on-chip peripherals and optimize system design.
Who Should Attend: Software and system engineers who need to come up to speed quickly on how to design with this architecture.
Participants will be provided: A hard copy of the workshop notes, lab book and textbook. A CDROM of all the lab experiments and demo version of the development tools is also provided.
Prerequisite: Knowledge/experience of some microprocessor/microcontroller is highly recommended.
Course Fees: $1500 per participant; Onsite training is to be negotiated with the customer