Course Title: MPC5777C (Cobra55nm) PowerPC Multi-Core Architecture
Target Applications: Automotive, aerospace, industrial, and commercial.
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Course Description: This 3 day course offers in-depth overview of the Multi-Core MPC5777C (Cobra55nm) device. Full coverage of the PowerPC cores is provided including Power Architecture main features, operation and Programming.
To ensure safety integrity level (ASIL) and meet ISO 26262 standards and requirements for critical applications, the Cobra device integrates two cores running in Lock-step with redundancy checkers for error and glitch detection along with End-to-End Error Correction Code (E2E) will be covered.
The course will cover the on-chip caches, memory management unit (MMU), system memory protection Unit (MPU), system Integration and chip pad configuration, system exception and handling, interrupt controller and external interrupts, boot assist module (BAM) and startup sequence for all on-chip processor cores.
Details of most of on-chip peripherals, such Deserial Serial Peripheral Interface (DSPI), eDMA engine, serial interfaces, periodic interrupt timers (PITs), system timers (STMs), watchdog timers (WDGs). It also covers the multiple on-chip RSD eQADCs and Sigma Delta SD_ADCs including decimation filter and eTPU reaction channels. The Enhanced Modular I/O System (eMIOS), and the Enhanced Time Processor Unit (eTPU2+) with some real application examples will be discussed.
Who Should Attend: Software and system engineers who need to come up to speed quickly on how to program and design with the MPC5777C Device.
Prerequisite: Knowledge/experience of some microprocessor/microcontroller is necessary.
After completing the course, the participant will understand the basic concepts of the MPC5777C device and all major functional blocks.
Clock Generation and Initialization