Course Title: MPC5777M (Matterhorn) PowerPC Multi-Core Architecture
Target Applications: Automotive, aerospace, industrial, and commercial.
Course Description: This 3 day course offers in-depth overview of the Multi-Core MPC5777M device. Full coverage of the on-chip PowerPC cores is provided including Power Architecture main features, operation and Programming. Two cores running in Lock-step to ensure safety integrity level (ASIL) requirements for safety critical applications.
The course covers the on-chip tightly-coupled memories including instruction and data caches, core memory management unit (CMPU), system memory protection Unit (SMPU), Low power management, system Integration and chip pad configuration, system exception, Interrupt controller and external interrupts, boot assist Flash (BAF) and startup sequence for all on-chip processor cores, semaphore unit (SEM4) which allows sharing of system resources to ensure data integrity and coherency, cross-bar switches to support simultaneous multi-master to multi-slave accesses.
Details of most of on-chip peripherals, such Deserial Serial Peripheral Interface (DSPI), micro-second channel (TSB), eDMA multiplexers and eDMA engine, serial interfaces, periodic interrupt timers (PITs), system timers (STMs), watchdog timers (WDGs). It also covers the multiple on-chip SAR_ADCs and SD_ADCs including trigger signals from GTM and other external signals. Full details of the Generic Timer Module (GTM) also covered.
Who Should Attend: Software and system engineers who need to come up to speed quickly on how to program and design with the MPC5777M Device.
Prerequisite: Knowledge/experience of some microprocessor/microcontroller is necessary.
After completing the course, the participant will understand the basic concepts of this quad core device and all major functional blocks.
Interrupt controller, architectural features and startup sequence
Memories, Analog and system timers
Generic Timer Module (GTM)