Syllabus

Day 1

• Tools Installation and Introduction. Step-by-step installation guide of ASH WARE's eTPU/eTPU2 C Compiler (ETEC) and ASH WARE's eTPU2+ DevTool. Brief tour of the IDE including stepping, breakpoints, examining trace data, measuring pulse widths using waveform window. Brief tour of the compiler including compiling, project files, multi-file projects, command line, and library directory. Student will modify some eTPU code to perform a calculation, compile, run in simulation and verify calculation.
• Channel Hardware Basics. A "C-centric" introduction to fundamental channel hardware concepts. Sampling input pin state versus detection of an edge and recording the time at which that edge occurred. Forcing an output pin to a state versus scheduling a output pin edge to occur at a particular future point in time.
• Events and Event Handling. The eTPU is an event servicing device. Using the eTPU compiler to create an event vector table. Examine event and thread response timing diagrams to see where event servicing occurs.

Day 2

• Channel Hardware Details. Step through each of the fields used to program the channel hardware. A step-by-step guide to setting up matches and transition detection.
• The Programming Model. Essentially a programmers' model chapter, with emphasis on context and thread issues. Key data type, function variables, explained in detail including memory map. Other miscellaneous issues.
• Basic Tools Issues. Automated testing using the IDE (simulation), including data flow, behavior verification, and code coverage. Auto-code generation in the Compiler solves two-copy problem. Example host-side drivers with auto-code generated from the Compiler.

Day 3

• Channel Hardware Modes. Explain details of match/transition and action unit A/B using the channel "mode". A problem-solving approach: "How to solve problem X? Use channel mode Y."? Includes the eTPU2 User Designed Channel Mode.
• Angle Mode/Motor Control. Angle mode hardware is a digital phase lock loop (PLL) with a software assist. Underlying concepts and details on the software assist. Motor control covers NXP's set 4 drivers.
• Scheduler. The round robin scheduler algorithm. Calculating worst case latency. Statistical latency analyses using post processing trace-dump files.

Day 4 (available upon request)

• Assistance with the architecture of a customer's design

Included with the course itself is a set of printed course notes that provide labs at the end of each chapter.