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MPC5676R (Cobra) Power Architecture

Target Applications

Automotive, commercial, industrial, and aerospace.

Course Description

This 3 day course offers coverage of e200z7 Dual Core Power Architecture, memory protection and memory controller, cross-bar switch, System Timers and all internal/external buses. Also included are details of all on-chip peripherals with software example demonstrations provided on some modules.

Who Should Attend

Software and system engineers who need to come up to speed quickly on how to program and design with the MPC567xR Devices.

Participants will be provided: A hard copy of the workshop course notes, lab book and textbook. A CDROM of all the example software projects and demo version of the development tools is also provided.


Knowledge/experience of some microprocessor/microcontroller is necessary.

After completing the workshop, the participant will understand the basic concepts of the Power Architecture and all major functional blocks of the MPC567xR devices.

Detailed Agenda

Day 1

  • MPC567xR Overview

  • Main Features and Road Map

  • Compatibility and Scalability

  • Power Architecture Coreand Programming Model (Z7 Core)

  • Classic PowerPC Instruction Set

  • Signal Processing Engine (ver. 1.1 and 2.0)

  • Power Architecture Exceptions and Interrupts

  • Interrupt Controller

  • Context Switching (New Instructions)

  • Dual Core basic operation and Programming

  • Memory Management Unit (MMU)

  • System Caches (with cache coherency support on MPC567xR)

  • Memory Protection Unit

  • Semaphore Block

Day 2

  • System Clock Generation and Initialization

  • PLL and System Clock Generation

  • Pad (Pin) Assignment and Configuration

  • Boot-assist Module (Boot Sequence) Device Configuration

  • System Reset Sources and Reset Handling

  • Power management

  • Power Modes

  • New Instructions

  • Software Watchdog Timer  (SWT)

  • System Timers (STM)

  • Periodic Interrupt Timers (PIT)

  • Software Initialization Checklist after Power and Resets

Day 3

  • Peripherals

  • Enhanced DMA (eDMA2)

  • Enhanced Modular I/O System (eMIOS200)

  • Enhanced Timer Processor Unit (eTPU2)

  • Queued A/D Converter (eQADC)

  • Decimation Filter

  • Enhanced Serial Communication Interface (eSCI) and LIN Bus

  • DSPI

  • FlexCAN2

  • Protected Port Output (on MPC567xR)

  • System Memory

  • Error Correction Code

  • SRAM

  • Flash Erase and Programming

  • CRC module (on MPC567xR)

  • Built In Self Test (on MPC567xR)

  • Tools

  • Nexus Summary

  • Development Trigger Semaphores (on MPC567xR)

  • Calibration

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