mpc56xxbcd Training

ASH WARE – Embedded Software Tools since 1994

Title:MPC56xxB/C/D (Bolero) Family Course

Target Applications: Automotive, commercial, industrial, and aerospace.

Course Description: This 4 day course offers detailed coverage of dual core architecture (e200z4 and e200z0) with emphasis on the main differences between the 2 cores. The execution units, programmer’s model, PowerPC Instruction Set Architecture (ISA) and variable-length encoding are covered.

System exceptions and Interrupt handling are fully covered on both cores with hands-on examples. Memory Management Unit (MMU) and Instruction Cache integrated on the PPC e200z4 core are fully discussed. Memory protection and memory controller, crossbar switch, power management, reset sources, boot-assist module and device modes are also covered.

The course includes details coverage of all on-chip peripherals, such as the enhanced eMIOS200, ADC, Cross Trigger Unit (CTU), system timers, FlexCAN, DSPI and SCI-LINFlex buses including the memory system and the error correction code (ECC). It also covers the dual core architecture and discusses synchronization issues between the 2 cores by enabling and utilizing the Semaphore Unit (SEM4) using some application examples.

The 4 day course includes complete coverage of the enhanced Direct Memory Controller (eDMA) and DMA multuiplexer.

Who Should Attend: Software and system engineers who need to come up to speed quickly on how to program and design with the MPC56xx Bolero Devices.

Participants will be provided: A hard copy of the workshop course notes, lab book and textbook. A CDROM of all the lab experiments and demo version of the development tools is also provided.

Prerequisite: Knowledge/experience of some microprocessor/microcontroller is necessary.

With hands-on provided and development tools, the participant will be able to program on-chip peripherals and be able to optimize system design.

After completing the 4 day workshop, the participant will understand the basic concepts of the Power Architecture and all major functional blocks of the MPC56xx devices. 

Detailed Agenda:

Day 1

  • Road Map and Main Features
  • System Overview
  • Power Architecture Coreand Programming Model (Z0 Core and Z4 Core)
  • PPC Instruction Set Architecture (ISA)
  • Variable Length Encoding
  • Dual Core Architecture (MPC564xC)
  • Semaphore Unit
  • Dual core examples

Day 2

  • Memory Management Unit (MMU) operation and programming
  • Instruction Cache
  • System exceptions and interrupt handling
  • Interrupt Controller (INTC)
  • Vector Table Implementations on e200z0 and e200z4 cores
  • Context Switching (New Instructions)
  • Wake Up module(WKUP)
  • Crossbar Switch
  • Memory Protection Unit
  • Frequency Modulated Phase Locked Loop module(FMPLL)
  • DMA Multiplexer
  • Enhanced Direct Memory Controller (eDMA)

Day 3

System Clock Generation and System Initialization

  • System Integration Unit (SIU)
  • Pad (Pin) Assignment and Configuration
  • Boot-assist Module (Boot Sequence) Device Configuration
  • System Reset Sources and Reset Handling
  • Mode Entry(MC_ME)
  • Power Management and Low Power Modes
  • Voltage Regulator(VREG)
  • Real Time Clock (RTC)
  • Periodic Interrupt Timer module(PIT)
  • System Timer (STM)
  • Timed Input Output module(eMIOS200)

Day 4

Serial Interfaces

  • Deserilize-Serial Peripherals Interface controller module(DSPI)
  • Serial Communications-LINFlex Interface modules(SCI-LINFlex)
  • Controller Area Network controller modules(FlexCAN)
  • FlexRay overview
  • Inter IC Controller modules(I2C)

Analog System

  • Analog to Digital Converter modules (ADC)
  • Cross Triggering Unit(CTU)

System Memory

  • Error Correction Code(ECC)
  • SRAM organization
  • Flash organization, programming and operation
  • Software Initialization Checklist after Power and Resets


  • Joint Test Action Group interface(JTAG)
  • Nexus Debug Interface module(NDI)
  • Calibration