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MPC5744P (Panther) Power Architecture

Target Applications

Automotive, Radar for Advanced Driver Assistance Systems, Aerospace and Safety Critical Applications.

Course Description

This 3 day course offers coverage of e200z4 Dual-Core Power Architecture, Core Memory Protection Unit, System Protection Unit (SMPU), Instruction and Data Caches, Crossbar switch and all Internal Buses, Redundancy Checker (CR), Fault Collection & Control Unit (FCCU), Clock Generation, Power Modes and Power Management Unit.

It covers two cores running in a delayed lock-step mode with emphasis on safety-critical features to meet Automotive Safety Integrity Level (ASIL-26262) standards.

The course provides lengthy discussion and coverage of the motor control peripheral set with emphasis on the FlexPWM, Cross Trigger Unit (CTU) and the Analogue-to Digital Converter (ADC) and how they interact with each other. It includes coverage of the Serial I/O Modules such as LINFlex, FlexCAN and DSPI interfaces, Enhanced Direct Memory Controller (eDMA) running in the delayed lock-step using the same methodology as the PPC processor cores.

The course will have hands-on lab examples using the MPC5744P Evaluation Boards (EVBs).

Who Should Attend

Software and system engineers who need to come up to speed quickly on how to program and design with the MPC5744P Device. Participants will be provided a hardcopy of the workshop course notes and lab book. A CDROM of all the lab experiments and demo version of the development tools is also provided.


Knowledge/experience of some microprocessor/microcontroller is necessary.

After completing the workshop, the participant will understand the basic concepts of the Dual Core Power Architecture and all major functional blocks of the Panther (MPC5744P) device.

Detailed Agenda

Day 1

MPC5744P Dual Core

  • Main Features

  • System Overview

  • Dual Core running in delayed lock-step

  • Redundancy Checkers

  • Power Architecture Core

    • Programming Model (e200z4 Core)

    • Classic PowerPC Instruction Set

    • Variable-Length Encoding (VLE)

  • Core Exceptions and Handling

  • Interrupt Controller

    • INTC Programmer’s Model

    • Context Switching (New Instructions)

    • Interrupts Handling

  • Core Memory Protection Unit (CMPU)

  • System Caches (Instruction and Data)

  • System Memory Protection Unit (SMPU)

  • Crossbar Switch

  • System Integration Unit (SIUL)

    • Pad Functional Description

    • Pad Assignment & Electrical Configuration

    • External Interrupts and eDMA Trigger Management

Day 2

  • System Clock Generation and Initialization

    • Internal Oscillator,

    • Phase Locked Loops (PLLs)

    • System Clock Generation

    • Clock Monitor Unit (CMU)

  • Boot-assist Module (Boot Sequence)

  • External Bus Interface (EBI)

  • System Reset Sources

    • Device Configuration

    • Reset Handling

  • Software Initialization Checklist after Power and system Resets

  • Two cores running in a clock-accurate lock-step mode (DPM)

    • Concept

    • Description

    • Detection and Correction

  • System Timers

    • Periodic Interrupt Timers (PIT)

    • STM

    • SWT

  • Serial I/O

  • UART and LINFlex Bus

  • DSPI

  • FlexCAN2

  • Flexray Overview

  • System Memory

    • SRAM

    • Flash Organization and operation

    • Erase and Program Sequence

    • Error Correction, Detection & Error Reporting

  • Enhanced DMA (eDMA2)

    • Functional operation and description

    • 2 DMA Engines running in delayed lock-step

Day 3

  • Motor Control Peripheral Set

    • eTimer      

    • FlexPWM Timer

    • A/D Converter (ADC)

    • Cross Trigger Unit (CTU)

  • Functional Safety

  • Tools

    • Nexus Summary

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