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MPC5777C (Cobra55nm) Multi-Core Architecture

Target Applications

Automotive, aerospace, industrial, and commercial.

Course Description

This 3 day course offers in-depth overview of the Multi-Core MPC5777C (Cobra55nm) device. Full coverage of the PowerPC cores is provided including Power Architecture main features, operation and Programming.

To ensure safety integrity level (ASIL) and meet ISO 26262 standards and requirements for critical applications, the Cobra device integrates two cores running in Lock-step with redundancy checkers for error and glitch detection along with End-to-End Error Correction Code (E2E) will be covered.

The course will cover the on-chip caches, memory management unit (MMU), system memory protection Unit (MPU), system Integration and chip pad configuration, system exception and handling, interrupt controller and external interrupts, boot assist module (BAM) and startup sequence for all on-chip processor cores.

Details of most of on-chip peripherals, such Deserial Serial Peripheral Interface (DSPI), eDMA engine, serial interfaces, periodic interrupt timers (PITs), system timers (STMs), watchdog timers (WDGs). It also covers the multiple on-chip RSD eQADCs and Sigma Delta SD_ADCs including decimation filter and eTPU reaction channels. The Enhanced Modular I/O System (eMIOS), and the Enhanced Time Processor Unit (eTPU2+) with some real application examples will be discussed.

Who Should Attend

Software and system engineers who need to come up to speed quickly on how to program and design with the MPC5777C Device.


Knowledge/experience of some microprocessor/microcontroller is necessary.

After completing the course, the participant will understand the basic concepts of the MPC5777C device and all major functional blocks.

Detailed Agenda

Day 1

MPC5777C Overview

  • Road Map

  • Architectural features

  • Two cores running in lock-step

  • Internal buses and End-to-End ECC

  • Redundancy and checkers

  • Multi-masters and cross bar switch

  • Core programming Model (e200z7 Core)

  • Classic PowerPC Instruction Set

  • Signal Processing Engine

  • Core Exceptions and I/O Interrupts

  • Interrupt Controller

  • Context Switching (New Instructions)

  • Dual Core basic operation and Programming

  • Semaphore unit (SEM4)

  • Memory Management Unit (MMU)

  • System Caches

  • Memory Protection Unit

  • Protected Port Output (on MPC567xR)

Day 2

Clock Generation and Initialization

  • PLL and System Clock Generation

  • Pad (Pin) Assignment and Configuration

  • Boot-assist Module (Boot Sequence) Device Configuration

  • System Reset Sources and Reset Handling

  • Software Initialization Checklist after Power and Reset

System Timers

  • Enhanced DMA (eDMA2)

  • Software Watchdog Timer (SWT)

  • System Timers (STM)

  • Periodic Interrupt Timers (PIT)

  • Enhanced Modular I/O System (eMIOS200)

  • Enhanced Timer Processor Unit (eTPU2)

Day 3


  • Queued A/D Converter (eQADC)

  • Decimation Filter

  • Reaction Module

  • Enhanced Serial Communication Interface (eSCI) and LIN Bus

  • DSPI

  • FlexCAN2

System Memory

  • Error Correction Code

  • SRAM

  • Flash Erase and Programming

  • PASS Security and Tamper Detection

  • CRC module

  • Built In Self-Test

  • Functional Safety


  • Nexus Summary

  • Development Trigger Semaphores

  • Calibration

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