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MPC57xx (Rainier & Fuji) Multi-Core Architecture

Target Applications

Automotive, aerospace, industrial, and commercial.

Course Description

This 4 day course offers in-depth overview of the Multi-Core MPC57xx devices with emphasis on Rainier(MPC5746R) and  Fuji(MPC574xF). The course offers full coverage of the on-chip PowerPC cores including two cores running in delayed lock-step to meet ISO26262 safety requirements.

It covers the on-chip tightly-coupled memories (TCMs) including instruction and data caches, core memory protection unit (CMPU), Crossbar switches, system buses and system memory protection Unit (SMPU), Low power management, system Integration and chip pad configuration.

Core exceptions, Interrupt controller and interrupt handling is also covered.

Boot assist Flash (BAF) and Mode Entry module along with startup sequence for all on-chip processor cores will be covered in details. To allow sharing of system resources and ensure data integrity and coherency, the semaphore unit is also covered along with cross-bar switches that support simultaneous multi-master to multi-slave accesses. Details of most of on-chip peripherals, such Deserial Serial Peripheral Interface (DSPI), micro-second channel (TSB), eDMA multiplexers and eDMA engine, serial interfaces, periodic interrupt timers (PITs), system timers (STMs), watchdog timers (WDGs). The course also covers the multiple on-chip SAR_ADCs and SD_ADCs including trigger signals from eTPU, eMIOS or GTM depending on SoC timer implementation.

A detailed overview of system timers: Enhanced Modular I/O System (eMIOS), Enhanced Time Processor Unit (eTPU) and Global Timer Module (GTM) will also be covered.

Those who interested in meeting the Automotive Integrity Level (ASIL 26262) safety standards will benefit from attending this training.

Who Should Attend

Software and system engineers who need to come up to speed quickly on how to program and design with the MPC5746M Device.


Knowledge/experience of some microprocessor/microcontroller is necessary.

After completing the workshop, the participant will understand the basic concepts of multi-core devices and all major functional blocks.

Detailed Agenda

Day 1

MPC57xx Family Roadmap Overview

  • Main Features and System Architecture

  • On-chip tightly-coupled memories including instruction and data caches

  • Level 2 memory organization and operation

  • Overlay memory functional description

  • Power architecture coresprogramming Model that covers (e200z419/z420 and z425 cores including variable-length encoding (VLE) and light signal processing unit (LSP)

  • Core memory protection unit (CMPU)

  • Crossbar switches and multi-bus master arbitration sequence

  • System memory protection unit (SMPU)

  • System buses

  • Power Architecture Exceptions and Interrupts

  • Interrupt Controller and Context Switching

  • Semaphore Block

Day 2

Architectural features and startup sequence

  • System Clock Generation and PLL operation

  • Pad (Pin) assignment and configuration

  • Boot-assist Flash (BAF boot sequence)

  • System Reset Sources and Reset Handling

  • Device configuration and system initialization at startup

  • Mode Entry Module (MC_ME) and low power Modes

  • DMA_Multiplexers

  • eDMA functional description and programming

Day 3

Serial Interfaces

  • DSPI

  • Microsecond channel (TSB)

  • CRC Generator

  • Introduction to FlexRay

  • CAN Bus


Day 4

Introduction to system timers

  • System timers (STMs), periodic interrupt timers (PITs) and watchdog

  • SAR_ADCs and SD_ADC architecture and operation

  • Enhance Modular I/O System (eMIOS)

  • Enhanced Time Processor Unit (eTPU)

  • Global Timer Module (GTM)

Functional Safety

Introduction to Functional Safety

Fault Control and Collection Unit (FCCU)

Self Test Control Unit (STCU2)

Meeting ASIL 26262 Standards


Nexus Summary

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